Graph methods for recognition of CMOS gates in transistor-level circuits
The paper focuses on the decompilation of a flat transistor circuit in SPICE format into a hierarchical network of logic gates. The problem arises in VLSI layout verification as well as in reverse engineering transistor circuit to redesign integrated circuit and to detect untrusted attachments. The...
| Published in: | Прикладная дискретная математика № 64. С. 43-55 |
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| Format: | Article |
| Language: | English |
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| Online Access: | http://vital.lib.tsu.ru/vital/access/manager/Repository/koha:001143251 |