APA (7th ed.) Citation

Cheremisinov, D. I., & Cheremisinova, L. D. Graph methods for recognition of CMOS gates in transistor-level circuits. Прикладная дискретная математика, 0210-48760(2024), .

Chicago Style (17th ed.) Citation

Cheremisinov, D. I., and L. D. Cheremisinova. "Graph Methods for Recognition of CMOS Gates in Transistor-level Circuits." Прикладная дискретная математика 0210-48760, no. 2024 ().

MLA (8th ed.) Citation

Cheremisinov, D. I., and L. D. Cheremisinova. "Graph Methods for Recognition of CMOS Gates in Transistor-level Circuits." Прикладная дискретная математика, vol. 0210-48760, no. 2024, .