Graph methods for recognition of CMOS gates in transistor-level circuits
The paper focuses on the decompilation of a flat transistor circuit in SPICE format into a hierarchical network of logic gates. The problem arises in VLSI layout verification as well as in reverse engineering transistor circuit to redesign integrated circuit and to detect untrusted attachments. The...
| Published in: | Прикладная дискретная математика № 64. С. 43-55 |
|---|---|
| Main Author: | |
| Other Authors: | |
| Format: | Article |
| Language: | English |
| Subjects: | |
| Online Access: | http://vital.lib.tsu.ru/vital/access/manager/Repository/koha:001143251 Перейти в каталог НБ ТГУ |
| LEADER | 02267nab a2200361 c 4500 | ||
|---|---|---|---|
| 001 | koha001143251 | ||
| 005 | 20240904180944.0 | ||
| 007 | cr | | ||
| 008 | 240904|2024 ru s a eng d | ||
| 024 | 7 | |a 10.17223/20710410/64/4 |2 doi | |
| 035 | |a koha001143251 | ||
| 040 | |a RU-ToGU |b rus |c RU-ToGU | ||
| 100 | 1 | |a Cheremisinov, D. I. |9 368650 | |
| 245 | 1 | 0 | |a Graph methods for recognition of CMOS gates in transistor-level circuits |c D. I. Cheremisinov, L. D. Cheremisinova |
| 246 | 1 | 1 | |a Графовые методы распознавания КМПО-вентилей в схемах транзисторного уровня |
| 336 | |a Текст | ||
| 337 | |a электронный | ||
| 504 | |a Библиогр.: 18 назв. | ||
| 520 | 3 | |a The paper focuses on the decompilation of a flat transistor circuit in SPICE format into a hierarchical network of logic gates. The problem arises in VLSI layout verification as well as in reverse engineering transistor circuit to redesign integrated circuit and to detect untrusted attachments. The most general case is considered when the extraction of functional level structure from transistor-level circuit is performed without any predetermined cell library. Graph methods for solving some key tasks in this area are proposed. The presented graph methods have been implemented in C++ as a part of a decompilation program, which has been tested using practical transistorlevel circuits. | |
| 653 | |a КМПО-схема из транзисторов | ||
| 653 | |a экстракция подсхем | ||
| 653 | |a распознавание логических вентилей | ||
| 653 | |a изоморфмзм графов | ||
| 653 | |a SPICE, формат | ||
| 655 | 4 | |a статьи в журналах |9 969733 | |
| 700 | 1 | |a Cheremisinova, L. D. |9 368651 | |
| 773 | 0 | |t Прикладная дискретная математика |d 2024 |g № 64. С. 43-55 |x 2071-0410 |w 0210-48760 | |
| 852 | 4 | |a RU-ToGU | |
| 856 | 4 | |u http://vital.lib.tsu.ru/vital/access/manager/Repository/koha:001143251 | |
| 856 | |y Перейти в каталог НБ ТГУ |u https://koha.lib.tsu.ru/cgi-bin/koha/opac-detail.pl?biblionumber=1143251 | ||
| 908 | |a статья | ||
| 039 | |b 100 | ||
| 999 | |c 1143251 |d 1143251 | ||