Testing digital circuits: studying the increment of the number of states and estimating the fault coverage
Testing of digital circuits is very important, especially for guaranteeing the correct and reliable functioning of electronic devices. One of the possibilities for deriving high quality test suites is using test generation methods for a corresponding Finite State Machine simulating the circuit b...
Published in: | 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM 2018), Erlagol, Altai Republic, 29 June - 3 July, 2018 : proceedings P. 220-224 |
---|---|
Other Authors: | Laputenko, Andrey V, López, Jorge, Kushik, Natalia G., Vinarskii, Evgenii |
Format: | Book Chapter |
Language: | English |
Subjects: | |
Online Access: | http://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000659775 Перейти в каталог НБ ТГУ |
Similar Items
-
On the fault coverage of high-level test derivation methods for digital circuits
by: López, Jorge -
Deriving tests with guaranteed fault coverage for finite state machines with timeouts
by: Tvardovskii, Aleksandr - FSM-based testing from user defined faults adapted to incremental and mutation testing
-
A practical approach for testing timed deterministic finite state machines with single clock
by: El-Fakih, Khaled -
Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults
by: Matrosova, Anzhela Yu